// Subcircuits for use in the AMI06 technology
simulator lang=spectre

subckt buffer Vdd Vss in out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
	I0 (Vdd Vss in temp) ccInverter
	I1 (Vdd Vss temp out) ccInverter
ends buffer

subckt ccInverter VDD VSS in out 
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
    MP (out in VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
        pd=3u+wp m=mult 
    MN (out in VSS VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
        pd=3u+wn m=mult
ends ccInverter

subckt tgate VDD VSS in out pass
parameters wp=3u wn =1.5u ln=600n lp=600n mult=1
   I3 (VDD VSS pass pass_inv) ccInverter
   N0 (in pass out VSS) ami06N w=wn l=ln as=2.25e-12 ad=2.25e-12 ps=6u \
           pd=6u m=mult region=sat
   P0 (out pass_inv in VDD) ami06P w=wp l=lp as=4.5e-12 ad=4.5e-12 ps=9u \
           pd=9u m=mult region=sat
ends tgate

subckt tGateMux VDD VSS in0 in1 select out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
   I0 (VDD VSS in0 out selectPrime) tgate mult=mult
   I1 (VDD VSS in1 out select) tgate mult=mult
   I2 (VDD VSS select selectPrime) ccInverter mult=mult
ends tGateMux

subckt mux4to1 in00 in01 in10 in11 out Select0 Select1 VDD VSS
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
   I0 (VDD VSS in00 in01 Select0 net75) tGateMux mult=mult
   I1 (VDD VSS in10 in11 Select0 net79) tGateMux mult=mult
   I2 (VDD VSS net75 net79 Select1 out) tGateMux mult=mult
ends mux4to1


subckt ccShifter A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 S0 S1 Vdd Vss
	I22 (Vdd Vss net223 out0) ccInverter
	I21 (Vdd Vss Vss net223) ccInverter
	mux8 (A7 A6 A5 A4 out8 S0 S1 Vdd Vss) mux4to1
	mux9 (A8 A7 A6 A5 out9 S0 S1 Vdd Vss) mux4to1
	mux10 (A9 A8 A7 A6 out10 S0 S1 Vdd Vss) mux4to1
	mux11 (A10 A9 A8 A7 out11 S0 S1 Vdd Vss) mux4to1
	mux15 (A14 A13 A12 A11 out15 S0 S1 Vdd Vss) mux4to1
	mux14 (A13 A12 A11 A10 out14 S0 S1 Vdd Vss) mux4to1
	mux13 (A12 A11 A10 A9 out13 S0 S1 Vdd Vss) mux4to1
	mux12 (A11 A10 A9 A8 out12 S0 S1 Vdd Vss) mux4to1
	mux4 (A3 A2 A1 A0 out4 S0 S1 Vdd Vss) mux4to1
	mux5 (A4 A3 A2 A1 out5 S0 S1 Vdd Vss) mux4to1
	mux6 (A5 A4 A3 A2 out6 S0 S1 Vdd Vss) mux4to1
	mux7 (A6 A5 A4 A3 out7 S0 S1 Vdd Vss) mux4to1
	mux3 (A2 A1 A0 Vss out3 S0 S1 Vdd Vss) mux4to1
	mux1 (A0 Vss Vss Vss out1 S0 S1 Vdd Vss) mux4to1
	mux2 (A1 A0 Vss Vss out2 S0 S1 Vdd Vss) mux4to1
ends ccShifter	
// End of subcircuit definition.
